1. Field of the Invention
The present invention generally relates to a method for trimming a carbon-containing film such as a photoresist at a reduced trimming speed, for spacer-defined double patterning (SDDP), for example.
2. Description of the Related Art
In semiconductor manufacturing processes, fine patterns for circuits, for example, are formed on a semiconductor wafer by etching such as plasma-assisted etching. Recently, formation of finer patterns has progressed by using spacer technology. As an example of such technology, spacer-defined double patterning (SDDP) is explained below. In the SDDP process, patterns are formed as core materials using photoresist or spin-on-carbon (SOC) at intervals which correspond to resolution limit, and then sidewall spacers are formed on sidewalls of the core materials. Thereafter, the core materials are removed while maintaining the sidewall spacers, and the remaining sidewall spacers are used as masks for etching an underlying layer. With this technology, because a distance between the spacers is smaller than a width of the sacrificing film such as photoresist, fine patterns can be formed in the underlying layer, which have a width narrower than the resolution limit.
In order to precisely control the critical dimension (CD), dimension control of the core materials is required, and for this purpose, trimming technology using plasma treatment, for example, is available for removing a portion of the core materials. For precise trimming, lowering trimming rate is essential so that the yield of precise spacers can be increased. In general, trimming rate can be reduced by reducing RF power applied for trimming. However, when RF power is too low, problems occur, e.g., generation of plasma becomes unstable, and in-plane plasma distribution becomes uneven, resulting in non-uniform in-plane trimming rate.
As an attempt for improving throughput and production economy, it is reported that formation of sidewall spacers and trimming are performed in the same process chamber. However, because optimal hardware required for these two processes is different, optimization of process conditions for the processes is a significant problem.
Any discussion of problems and solutions involved in the related art has been included in this disclosure solely for the purposes of providing a context for the present invention, and should not be taken as an admission that any or all of the discussion were known at the time the invention was made.